Mar
24
Call for Papers: DAIES Workshop @ SafeComp 2026
March 24, 2026 | | Comments Off on Call for Papers: DAIES Workshop @ SafeComp 2026
We are pleased to announce the Call for Papers for the DAIES Workshop 2026, co-located with SafeComp 2026, to be held in Valencia, Spain, with Joaquรญn Gracia acting as Workshop Organizer.
About the workshop
This workshop will provide a focused forum on how to design, verify, and certify AI-enabled embedded systems while preserving their overall dependability, including safety, reliability, availability, and security, under tight resource and real-time constraints. It targets AI-enabled embedded and cyber-physical systems deployed in safety-critical domains such as automotive, rail, aerospace, robotics, medical devices, and industrial control. The workshop will emphasize how functional safety, cybersecurity, and sustainability jointly contribute to system dependability when AI models, often opaque and non-deterministic, are deployed on constrained embedded platforms exposed to both accidental faults and malicious attacks.
Call for Papers
Researchers and practitioners are invited to submit original contributions presenting novel ideas, work-in-progress, or practical experiences related to the workshop topics. Workshops at SafeComp offer a collaborative environment to exchange ideas and discuss emerging challenges in safety, reliability, and sustainability of critical systems.
Topics of interest include (but are not limited to):
- Safe architectures and engineering approaches: Design and standards-compliant deployment of AI in embedded and cyber-physical systems.
- Verification, validation, and resilience: Testing, robustness, and fault-tolerance methods for reliable AI in constrained environments.
- Security, monitoring, and lifecycle management: Safety-security co-engineering, runtime monitoring, and continuous assurance of AI systems.
- Applications, tools, and evidence: Real-world case studies and resources for evaluating trustworthy AI in embedded systems.
Accepted full workshop research papers will be included in the complementary book of the SafeComp 2026 Proceedings. Templates for paper preparation can be downloaded from: https://www.springer.com/gp/computer-science/lncs/conference-proceedings-guidelines.
Important Dates
- Paper submission: 4 May 2026.
- Notification of acceptance: 18 May 2026.
- Camera-ready papers: 8 June 2026.
- Workshop date: 22 September 2026 (co-located with SafeComp 2026).
Join Us
DAIES 2026 aims to bring together researchers, industry experts, and practitioners to advance the state of the art in safe and reliable AI-enabled systems. We encourage you to contribute and be part of this exciting discussion.
We look forward to your submissions!
More information: https://safecomp2026.webs.upv.es/daies-2026/
Mar
5
๐๐ถ๐ป๐ฎ๐น ๐๐ฎ๐น๐น ๐ณ๐ผ๐ฟ ๐ฃ๐ฎ๐ฝ๐ฒ๐ฟ๐: ๐ฆ๐ฎ๐ณ๐ฒ๐๐ผ๐บ๐ฝ ๐ฎ๐ฌ๐ฎ๐ฒ!
March 5, 2026 | | Comments Off on ๐๐ถ๐ป๐ฎ๐น ๐๐ฎ๐น๐น ๐ณ๐ผ๐ฟ ๐ฃ๐ฎ๐ฝ๐ฒ๐ฟ๐: ๐ฆ๐ฎ๐ณ๐ฒ๐๐ผ๐บ๐ฝ ๐ฎ๐ฌ๐ฎ๐ฒ!
The deadline to submit your research on ๐๐ฎ๐ณ๐ฒ๐๐-๐ฐ๐ฟ๐ถ๐๐ถ๐ฐ๐ฎ๐น ๐๐๐๐๐ฒ๐บ๐ to a European top conference is just around the corner. We want to see your work in Valencia!
โณ Only 4 days left for abstract submission!
๐
๐๐ฒ๐ ๐๐ฎ๐๐ฒ๐:
โข Abstract Submission: 8 ๐ ๐ฎ๐ฟ๐ฐ๐ต
โข Full Paper Submission: 15 ๐ ๐ฎ๐ฟ๐ฐ๐ต
Hosted by Universitat Politรจcnica de Valรจncia (UPV) in the beautiful city of Valencia, SafeComp 2026 is the place to be this late September. Beyond the top-tier technical program, we are preparing an epic social program to make the most of the historic and modern Valencia, its weather, and the Mediterranean sea. โ๏ธ๐
Don’t miss one of Europe’s flagship events for researchers and industrial practitioners interested in the latest advances related toย ๐ฆ๐ฎ๐ณ๐ฒ, ๐ฅ๐ฒ๐น๐ถ๐ฎ๐ฏ๐น๐ฒ, ๐ฎ๐ป๐ฑ ๐ฆ๐ฒ๐ฐ๐๐ฟ๐ฒ computer-based systems!
https://safecomp2026.webs.upv.es/
Feb
25
LinkedIn for GSTF
February 25, 2026 | | Comments Off on LinkedIn for GSTF
We have a new LinkedIn page for the GSTF, available in this link.
Feb
20
NeuroAI4Space news published by UPV’s Instituto ITACA and RUVID
February 20, 2026 | | Comments Off on NeuroAI4Space news published by UPV’s Instituto ITACA and RUVID
UPV’s ITACA and RUVID Announce Advanced AI for Aerospace Platforms
The Universitat Politรจcnica de Valรจncia (UPV) through its ITACA Institute and RUVID has published the beginning of NeuroAI4Space.
These news can be accesed here and here.
Feb
18
Learning object available
February 18, 2026 | | Comments Off on Learning object available
The learning object โFallos hardware y su influencia en la confiabilidad de redes neuronalesโ is now available.
Authored by J. Gracia-Morรกn, this learning resource explores hardware faults and their impact on the reliability of neural networks, offering valuable insights for students, researchers, and professionals working in dependable systems, artificial intelligence, fault tolerance and embedded systems.
๐ Reference:
J. Gracia-Morรกn, โFallos hardware y su influencia en la confiabilidad de redes neuronalesโ, learning object, February 2026.
Available at: https://riunet.upv.es/handle/10251/232543
We invite you to explore this resource and share it with colleagues and students interested in neural network reliability and hardware fault analysis.
Feb
18
NeuroAI4Space LinkedIn
February 18, 2026 | | Comments Off on NeuroAI4Space LinkedIn
It is available the LinkedIn page of the NeuroAI4Space in this link.
Feb
17
Driving the Future of Space Innovation: NeuroAI4Space Project Receives IVACE+i Funding
February 17, 2026 | | Comments Off on Driving the Future of Space Innovation: NeuroAI4Space Project Receives IVACE+i Funding
The aerospace sector is taking a major step toward smarter, more autonomous systems. The NeuroAI4Space project, led by Intigia, has received funding from Instituto Valenciano de Competitividad e Innovaciรณn (IVACE+i) under the FEDER Comunitat Valenciana 2021โ2027 programme.
NeuroAI4Space aims to integrate advanced artificial intelligence capabilities directly into aerospace platforms such as satellites and drones. By enabling onboard data processing through neuromorphic AI hardware, these systems can reduce data transmission needs, optimize energy consumption, and operate with greater autonomy.
The project brings together a strong consortium including EMXYS, Universitat Politรจcnica de Valรจncia, and University of Alicante, combining expertise in edge AI, space-grade electronics, and fault-tolerant systems.
By embedding efficient, low-power AI directly into aerospace hardware, NeuroAI4Space strengthens the Valencian innovation ecosystem and positions Spain at the forefront of intelligent space technologies.
Jan
29
SAFECOMP 2026 Call for Workshops proposals
January 29, 2026 | | Comments Off on SAFECOMP 2026 Call for Workshops proposals
SAFECOMP 2026
45th International Conference on Computer Safety, Reliability and Security
September 22 to 25, 2026, Valencia, Spain
The 45th edition of the International Conference on Computer Safety, Reliability and Security (SafeComp 2026), to be held in Valencia in next September, will focus on the theme โEngineering safe and sustainable computing systemsโ, addressing the challenge of combining safety, security and sustainability in computing infrastructures. Founded in 1979, this conference brings together experts to share advances, experiences, and trends in the safety, reliability, and sustainability of critical systems.
SafeComp 2026 invites proposals for co-located workshops that will complement the main symposium by offering forums for focused discussions on emerging and specialized topics of safety, reliability, and sustainability of critical systems. Workshops may serve as platforms for early-stage idea exchange, in-depth research discussions, work-in-progress reports from research projects, or collaborative working sessions to address current challenges in the field.
Workshops are expected to attract both academic and industrial participants, including researchers, practitioners, and students. Accepted full workshop papers (6 โ 12 pages), reviewed according to Springer LNCS guidelines by at least three independent reviewers would be published in the SafeComp 2026 Workshops Proceedings. All workshops will be celebrated in parallel on September 22nd, ahead of the main conference. Authors of workshop papers are kindly invited to participate in the SafeComp main conference.
Submission Guidelines for Workshops Proposals
Prospective workshop organizers should submit a 2 to 3 – page proposal including:
- Workshop Title
- Description: goals, scope, relevance to SafeComp, and intended audience.
- Workshop Format: e.g., full/short paper presentations, posters, invited talks, panels, demos, hands-on sessions, etc.
- Submission & Review Process: details on paper length, review criteria, and promotional strategies (general Springer LNCS rules to apply for publishing).
- Duration: half-day or full day.
- History: information about previous editions (if applicable).
- Workshop Committee: short bios of the main workshop chairs, previous experience in similar roles, and a tentative list of Workshop Program Committee members.
Workshop Proposal Submission Deadline:ย ย ย ย ย ย ย 23 February 2026
Notification of Acceptance: ย ย ย ย ย ย ย ย ย ย ย ย ย ย ย ย ย ย ย ย ย ย ย ย ย ย ย ย ย ย 20 March 2026
Proposals should be submitted via email to safecomp2026-workshops @ upv.es and erwin.schoitsch @ ait.ac.at.
Jan
20
SAFECOMP 2026 Call for Papers
January 20, 2026 | | Comments Off on SAFECOMP 2026 Call for Papers
The call for papers for SAFECOMP 2026, which will be held this coming September at the UPV, is now available:
SAFECOMP 2026, 22-25 September 2026, Valencia (Spain)
The theme of SAFECOMP 2026 is โEngineering safe and sustainable computing systemsโ Society increasingly depends on interconnected systems of systems – combining cyber-physical infrastructures, industrial platforms, edge and cloud computing, and AI-enabled services – across domains such as mobility, healthcare, industry and agriculture. These systems not only provide the services that are essential for our lives but also pose unprecedented safety challenges. SafeComp 2026 focuses on engineering approaches to manage safety amid growing complexity, cybersecurity threats and pressing ecological concerns, ensuring that the computing systems remain sustainable and viable in the long term.
SAFECOMP 2026 solicits two types of paper submission (in both cases, up to 14 pages including bibliography):
– Research papers address a research gap and illustrate how the contribution submitted can help improve the state-of-the-art by advancing current knowledge;
– Practical experience reports / tool descriptions provide new insights and valuable support to practitioners. Papers exceeding the page limit will be excluded from the review process.
All papers will be reviewed by at least three members of the International Programme Committee. Papers must not have been previously published or concurrently submitted elsewhere.
All paper submissions must be formatted according to the LNCS templates provided by Springer. Abstracts and papers should be submitted in PDF through Easychair: https://easychair.org/conferences?conf=safecomp2026
===========
Important Dates
===========
– Abstract Submission: February 16, 2026
– Full Paper Submission: February 27, 2026
– Author Notification: April 24, 2026
===========
Topics of interest
===========
The conference covers all aspects related to the development, assessment, operation, and maintenance of safety-critical computer systems. Major topics include, but are not limited to:
– Distributed and real-time monitoring and control
– Fault-tolerant and resilient hardware and software architectures
– Fault detection and recovery mechanisms
– Security and privacy protection mechanisms for safety applications
– Safety guidelines and standards
– Safety/security co-engineering and trade-offs
– Safety and security qualification, quantification, assurance and certification
– Threats and vulnerability analysis
– Risk assessment in safe and secure systems
– Dependability analysis using simulation and experimental measurement
– Model-based analysis, design, and assessment
– Formal methods for verification, validation, and fault tolerance
– Testing, verification, and validation methodologies and tools
– Multi-concern dependability assurance and standardisation
– Domains: railways, automotive, space, avionics, process industries, IoT, highly automated and autonomous systems
=============
Application domains
=============
Relevant domains of application are, but are not limited to:
– Railways, automotive, space, avionics & process industries
– Highly automated and autonomous systems
– Telecommunication and networks
– Safety-related applications of smart systems and IoT
Jan
12
Paper accepted at ACM Transactions on Reconfigurable Technology and Systems
January 12, 2026 | | Comments Off on Paper accepted at ACM Transactions on Reconfigurable Technology and Systems
The paper entitled “An open-source methodology to emulate transient faults in ASIC storage cells using AMD Ultrascale+ FPGAs”, written by Ilya Tuzov, David de Andrรฉs, Juan Carlos Ruiz and Carles Hernรกndez has been accepted at ACM Transactions on Reconfigurable Technology and Systems
Abstract
The dependability assessment of critical systems must consider the emulation of transient faults, as they pose an important dependability threat for modern VLSI designs. FPGA-based systems are dominated by bit-flips in configuration memory (CM), which are relatively easy to emulate using partial runtime reconfiguration (RTR) FPGA fault injection (FFI) approaches. However, when FPGA is used as an ASIC prototyping platform, transient fault models representative of ASIC designs must be considered, such as bit-flips in sequential logic cells (Flip-Flops and on-chip RAM blocks). Existing RTR-FFI approaches do not adequately cover these faults, as they require the orchestrated manipulation of multiple CM bits for each target logic cell, and the location of these CM bits is unknown (not documented) for modern FPGA generations. This work experimentally formalises the mapping of the necessary CM bits, proposes an enhanced RTR-FFI methodology to emulate bit-flips in registers and on-chip RAMs of current-generation AMD Ultrascale+ FPGAs, and provides an upgraded publicly available open-source FFI tool (BAFFI: https://gitlab.com/selene-riscv-platform/DAVOS) supporting the proposed methodology. The validity of the proposed FFI approach is demonstrated by comparison with gate-level simulation-based fault injection in a case study of two soft-core processors (MC8051 and NOEL-V).