Jan
9
Paper available
January 9, 2026 | | Comments Off on Paper available
The paper entitled “Dependability analysis of neural networks implemented in Arduino”, written by Joaquรญn Gracia-Morรกn, Juan Carlos Ruiz Garcรญa, David De Andrรฉs, Luis-J. Saiz-Adalid, Juan C. Baraza,
Daniel Gil and Pedro Gil Vicente, and published in proceedings of the Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2025) is available to download from here.
Abstract
The use of neural networks has expanded to environments as diverse as medical systems, industrial devices and space systems. In these cases, it is essential to balance performance, power consumption, and silicon area. Furthermore, in critical environments, it is necessary to ensure high fault tolerance.
Traditionally, the parameters of neural networks have been codified using 32-bit floating-point numbers, which entails high memory consumption and greater vulnerability to failures due to the aggressive scaling of CMOS technology. An effective strategy for optimizing these systems is to reduce parameter precision, using fewer bits and thus, reducing both the amount of memory required and the processing time.
However, several questions arise when implementing these types of networks in embedded systems: Do they maintain their reliability in critical environments, or do they require fault tolerance mechanisms? Are area and latency really reduced?
This work addresses these questions by reducing the precision of a neural network and implementing it in an Arduino-based system. In addition, Error Correction Codes have been incorporated and, using the fault injection technique, their reliability has been evaluated by comparing the same neural network with parameters encoded in 8, 16 and 32 bits.
Keywords
Error Correcting Codes, Dependability, Single Faults, Multiple Faults, Optimized Neural Networks, Embedded Systems
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